In synchronous electronic systems, the integrated circuits in the system are synchronized to a common reference clock. This synchronization often cannot be achieved simply by distributing a single reference clock to each of the integrated circuits for the following reasons, among others. When an integrated circuit receives a reference clock, the circuit often must condition the reference clock before the circuit can use the clock. Usually, a delay locked loop (DLL) has at least one delay element and a control circuit to provide the time delay as required, so as to synchronize the local clock to the reference clock. For example, as shown in FIG. 1, in a memory interface between a DDR (Double Data Rate) memory and a chipset, a clock cycle of DQS (data strobe) signal and a clock cycle of DQ (data) signal passed from the DDR memory to the chipset should be ideally aligned with each other. In this case, a DLL circuit will be used for phase-shifting the DQS signal by a certain delay for accurately latching the data.
As mentioned above, the DLL circuit is commonly used in integrated circuit, accordingly, there is a need for an improved DLL circuit, which synchronizes input clocks to reference clocks with a linear delay timing performance.